Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Give the formula for the average access time experienced by the processor in a system with 2 levels of caches.
Ans: Formula is for the average access time experienced by the processor in a
system having two levels of caches is described follow:
tave = h1C1+(1-h1)h2C2+(1-h1)(1-h2)M
h1=> hit rate in the L1 cache
h2= > hit rate in the L2 cache
M=> it's time to access information in the main memory
C1=> it's for time to access information in the L1 cache
C2=> it's for time to access information in the L1 cache
Explain Hit and Miss?
Ans. The performance of cache memory is often measured in terms of a quantity is said hit ratio. When the CPU refers to memory and finds the word in cache, it is said hit. If the word is not found in cache, then it is in primary memory and it counts as a miss.
What is configuration? Turing machine computes, changes occur in the current state, the current tap contents and the current head location. A setting of the
A managed bean - sometimes simply referred to as an MBean - is a type of JavaBean, developed with dependency injection. Managed Beans are particularly used in the Java Management E
How many address bits are required to represent 4K memory ? Ans. 12 address bits are required for representing 4K memory, as 4K = 2 2 x 2 10 = 2 12 Therefore 1K = 1024
Commutatively of Connectives You will be aware from the fact that some arithmetic operators have a property that it does not matter which way around you give the operator input
Q. Explain working of Digital Versatile Disk? With the capacious digital versatile disk (DVD) electronics industry has ultimately found an acceptable replacement for videotape
i want to know complete detail of 8086 microprocessor such as memory segment ,interface with ram rom ect
Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is initialized with the system bus. Classic DRAM has an asynchronous interface, which m
Explain Flash devices It is possible to read the contents of a one cell, but it is only possible to write an whole block of cells Greater density which leads to superior cap
What factors influences the bus design decisions? 1. Data Location: Device selection, address of data with in device( track, sector etc) 2. Data transfer: Amount, rate to
Artificial Intelligence Agents: We introduced what we'll be conversation about in Artificial Intelligence and why those things are necessary. This discussion is of course abou
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd