Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
Give the formula for the average access time experienced by the processor in a system with 2 levels of caches.
Ans: Formula is for the average access time experienced by the processor in a
system having two levels of caches is described follow:
tave = h1C1+(1-h1)h2C2+(1-h1)(1-h2)M
h1=> hit rate in the L1 cache
h2= > hit rate in the L2 cache
M=> it's time to access information in the main memory
C1=> it's for time to access information in the L1 cache
C2=> it's for time to access information in the L1 cache
Explain Hit and Miss?
Ans. The performance of cache memory is often measured in terms of a quantity is said hit ratio. When the CPU refers to memory and finds the word in cache, it is said hit. If the word is not found in cache, then it is in primary memory and it counts as a miss.
Ferroelectric RAM is a random-access memory same in construction to DRAM but uses a ferroelectric layer rather of a dielectric layer to achieve non-volatility. FeRAM is one of a gr
Why address bus is unidirectional and data bus is bidirectional? Ans) Because there is no require address transaction among processor and peripheral device but data bus is req
Interrupt handling: Handling Interrupts Several situations where the processor should avoid interrupt requests Interrupt-enable Interrupt-disable Typical
Q. Explain about FAT - Inode? Today modern PC comprises total capacity of nearly 40GB for storage of program and data Due to this huge capacity in place of having just one oper
How many flip-flops are required to construct mod 30 counter ? Ans. Mod - 30 counter +/- requires 5 Flip-Flop as 30 5 . Mod - N counter counts overall ' N ' number of state
OPPORTUNITIES AND THREATS IN COMPUTER FEILD
We have multiple instances in RTL (Register Transfer Language), do you do anything special during synthesis stage? Whereas writing RTL(Register Transfer language),say in Verilo
Performance of Pipelines with Stalls: A stall is reason of the pipeline performance to degrade the ideal performance. Average in
What are Parallel Algorithms? The central assumption of the RAM model does not hold for some newer computers that can implement operations concurrently, i.e., in parallel algor
When should I use server session pools and connection consumers? Ans) WebLogic JMS executes an optional JMS facility for defining a server-managed pool of server sessions. This
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd