Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
One of the simplest circuits is the asynchronous or ' ripple' counter. Below is shown the circuit diagram of a simple 3 stage ripple counter.
The operation of this circuit is based on the fact that the truth table for the JK flip flop is only valid if the clock waveform is falling, i.e. 1->0. Assume the outputs are all zero, the flip flops will not change until the clock on each flip flop falls. The clock in waveform has just fallen ,since the JKa inputs are logic '1' the device will toggle and the output will invert i.e. Qa=1. Flip flop B will not change because the clock waveform on B has risen (0->1) and these devices only functions on a falling edge. The clock in waveform has fallen again, so Qa toggles again (i.e. Qa =0), this has just produced a falling clock on JKb and Qb toggles (i.e. Qab=1) .The device has just counted from 000-> 001->010.
The circuit is called a ripple counter because the clock pulse is slowly rippling through the JK's, hence asynchronous (Not at the same time!) .The limitations of the asynchronous counter is the speed of operation. A rough formula for the maximum speed is when the clock changes before the output changes i.e. F = 1 / n x propagation delay where n = number of stages, propagation delay of one JK
A better technique is to use a synchronous design where all the JK are clocked together so the maximum frequency is only limited by the propagation delay of 1 JK.
The circuit appears to be complex in design, however it is easily realised by using state diagrams. The maximum frequency of operation is again roughly calculated by considering the frequency at which the output just changes before the clock in changes. F = 1/ Propagation delay
Q. (a) Draw the logic diagram of the enabled D latch using only NAND gates. (b) Complete the timing diagram of Figure (a) of theDlatchwhose block diagram and truth table are giv
Q. What are the Display Devices? Display devices can be categorized as on/off indicators, numeric, alphanumeric, or graphical displays. They may also be classified as active an
Q. What do you mean by Counters? The shift register can be used as a counter because the data are shifted for each clock pulse. A counter is a register that goes through a pred
Change Management in Power Distribution: Organisational change might be described as an organisation-wide effort to augment the effectiveness of an organisation through str
Define Shifting and Reversing – Linear System? The signal x[n - m] is said to be time-shifted by m samples, where m is an integer. If m is positive, the shift is to the right (
hi I need information of Compressor Shaft Impellers Coupling Hub Thrust Collars Balance Drum for centrifugal compressor with pecture
what is event triggering related to digital storage oscilloscope?
Q. explain the architecture of SS7 and compare with seven-layer OSI architecture. Ans: A block schematic diagram of CCITT no. 7 signalling system is displayed in figure. Sig
Q. What do you mean by Byte? Without question, the most vital data structure used by the 80x86 microprocessor is the byte this is true since the ASCII code is a 7-bit non-weigh
Q. What do you understand by common control? In some switching systems, control subsystem may be an integral part of switching network itself. Such system iscalled direct contr
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd