Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
One of the simplest circuits is the asynchronous or ' ripple' counter. Below is shown the circuit diagram of a simple 3 stage ripple counter.
The operation of this circuit is based on the fact that the truth table for the JK flip flop is only valid if the clock waveform is falling, i.e. 1->0. Assume the outputs are all zero, the flip flops will not change until the clock on each flip flop falls. The clock in waveform has just fallen ,since the JKa inputs are logic '1' the device will toggle and the output will invert i.e. Qa=1. Flip flop B will not change because the clock waveform on B has risen (0->1) and these devices only functions on a falling edge. The clock in waveform has fallen again, so Qa toggles again (i.e. Qa =0), this has just produced a falling clock on JKb and Qb toggles (i.e. Qab=1) .The device has just counted from 000-> 001->010.
The circuit is called a ripple counter because the clock pulse is slowly rippling through the JK's, hence asynchronous (Not at the same time!) .The limitations of the asynchronous counter is the speed of operation. A rough formula for the maximum speed is when the clock changes before the output changes i.e. F = 1 / n x propagation delay where n = number of stages, propagation delay of one JK
A better technique is to use a synchronous design where all the JK are clocked together so the maximum frequency is only limited by the propagation delay of 1 JK.
The circuit appears to be complex in design, however it is easily realised by using state diagrams. The maximum frequency of operation is again roughly calculated by considering the frequency at which the output just changes before the clock in changes. F = 1/ Propagation delay
A communication system for a voice-band (3 kHz) channel is designed for a received SNR E b /N 0 at the detector of 30 dB when the transmitter power is Ps =-3 dBW. Find the value o
Q. For the circuits shown in Figure, sketch the frequency response (magnitude and phase) of ¯V out / ¯V in .
Discuss the DWORD assembler directive with example. DWORD: This defines word type variable. The described variable may have one or more initial values into the dire
Disadvantages
Q. A current of 65 A is measured with an analog ammeter having a probable error of ± 0.5% of full scale of 100 A. Find the maximum probable percentage error in the measurement.
1. Name the three parts of a programmable logic controller (PLC) and explain why the PLC is preferred by designers over electromechanical relays. 2. Medium-voltage circuit break
For a 50kW three phase rectifier connected at 415 V to a point of common coupling with a short circuit capacity 500kVA modelled as an inductive source, design filters to make the s
Q. For the NOR and inverter realizations shown in Figure, find the truth table, the type of gate realized, and the expression for the logic output, in each case.
Theoretical calculations The characteristics of the d.c. machine you will be investigating are given on the last page of this part. Use 200V DC supply for both armature and fie
find the resultant of two forces 20N and25N acting at an angle 60 degree each other
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd