Already have an account? Get multiple benefits of using own account!
Login in your account..!
Remember me
Don't have an account? Create your account in less than a minutes,
Forgot password? how can I recover my password now!
Enter right registered email to receive password!
One of the simplest circuits is the asynchronous or ' ripple' counter. Below is shown the circuit diagram of a simple 3 stage ripple counter.
The operation of this circuit is based on the fact that the truth table for the JK flip flop is only valid if the clock waveform is falling, i.e. 1->0. Assume the outputs are all zero, the flip flops will not change until the clock on each flip flop falls. The clock in waveform has just fallen ,since the JKa inputs are logic '1' the device will toggle and the output will invert i.e. Qa=1. Flip flop B will not change because the clock waveform on B has risen (0->1) and these devices only functions on a falling edge. The clock in waveform has fallen again, so Qa toggles again (i.e. Qa =0), this has just produced a falling clock on JKb and Qb toggles (i.e. Qab=1) .The device has just counted from 000-> 001->010.
The circuit is called a ripple counter because the clock pulse is slowly rippling through the JK's, hence asynchronous (Not at the same time!) .The limitations of the asynchronous counter is the speed of operation. A rough formula for the maximum speed is when the clock changes before the output changes i.e. F = 1 / n x propagation delay where n = number of stages, propagation delay of one JK
A better technique is to use a synchronous design where all the JK are clocked together so the maximum frequency is only limited by the propagation delay of 1 JK.
The circuit appears to be complex in design, however it is easily realised by using state diagrams. The maximum frequency of operation is again roughly calculated by considering the frequency at which the output just changes before the clock in changes. F = 1/ Propagation delay
Q. In an RLC series circuit excited by a voltage source v(t), for R = 10 , L = 1 H, and C = 0.1F, determine v(t) if the capacitor voltage vC(t) = 5e -10t V.
Q. Explain the construction of depletion MOSFET? A slab of p-type material is formed from a silicon base and it is referred to as the substrate. It is the foundation upon which
Describe the process control instructions STC - It sets the carry flag & does not affect any other flag CLC - it resets the carry flag to zero &does not affect any other fl
Q. Prove mathematically that the operating point does not depend on beta, in a potential divider bias circuit ? To determine the operating point, consider the input section of
Question: (a) Explain the types of hazards in a 5 stage pipeline. (b) Describe the three RAW dependencies in the following instructions. i: R7←R12+R15 i + 1: R8←R7-R1
DC chopper This is one stage conversion device which is used for direct conversion of fixed de voltage at a level to an adjustable dc voltage at another level.
Lack of Accountability - High Technical Usage In huge, complex and widespread ST&D networks such as ours, the subsequent factors pose problems in arriving at reasonable estima
Determine the i-v characteristic of the network shown in Figure by the use of breakpoint analysis.
Critical Rate of Rise of Current The maximum rate of increase of current during on state which the SCR can tolerate is called the critical rate of rise of current f
(a) Consider the following transmission line with the reactance X1 placed across the input. It is being driven with a frequency ω such that the length of the line is λ/4. W
Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!
whatsapp: +91-977-207-8620
Phone: +91-977-207-8620
Email: [email protected]
All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd