Associative array processing, Computer Engineering

Assignment Help:

Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed below:

331_Associative Array Processing.png

Assume that we want to find the age and ID number of Ravi. If we use conventional RAM, it is essential to give the exact physical address of entry associated to Ravi in the instruction access entry such as:

    READ ROW 3

Another alternative idea is that we explore the whole list by means of the Name field as an address in instruction like:

    READ NAME = RAVI

Again with serial access memory this option may be implemented simply but it's a very slow process. An associative memory assists at this point and concurrently examines all the entries in the list and returns the desired list very rapidly. SIMD array computers have been developed with associative memory. This memory is content addressable memory by which it's meant that multiple memory words are accessible concurrently. The parallel accessing feature support parallel search and parallel compare too. This ability can be used in numerous applications like:

  • Radar signal tracking
  • Image processing
  • Artificial Intelligence
  • Retrieval and Storage of databases that are changing rapidly

The inherent parallelism characteristic of this memory has huge advantages and impact in parallel computer architecture. The associative memory is expensive compared to RAM. The array processor built with associative memory is termed as Associative array processor. In this section we explain a number of categories of associative array processor. Kinds of associative processors are based on organisation of associative memory. So first we discuss about associative memory organisation.


Related Discussions:- Associative array processing

Interconnection network, Interconnection Network Introduction Th...

Interconnection Network Introduction This unit discusses the types and properties of interconnection networks.  In multiprocessor systems, there are multiple I/O modules

Logic gates required to build a half adder, What are the gates required to ...

What are the gates required to build a half adder ? Ans. The gates needed to build a half adder are EX-OR gate and AND gate as shown below the logic diagram of half adder:

Mobility management in mobile systems, Instruction 1. You can do this i...

Instruction 1. You can do this individually or in groups of 2-3 students. 2. Any material copied and pasted from anywhere (e.g., figures and text) is considered plagiarism even

Basic tradeoff of concerns for instruction set design, Q. Basic Tradeoff of...

Q. Basic Tradeoff of concerns for instruction set design? Basic Tradeoff: Smaller instruction (less space) vs. desire for more powerful instruction repertoire. Generally p

How do you debug a loadrunner script, VuGen have two options to help debug ...

VuGen have two options to help debug Vuser scripts-the Run Step by Step command and breakpoints. The Debug settings in the Options dialog box permit us to verify the extent of the

Differentiate between intranet and internet, Differentiate between intranet...

Differentiate between intranet and internet Some comparisons between intranet and internet include: -  INTERNET is INTERnational NETwork -  An INTRANET is INTernal Restri

Application and function areas - artificial intelligence, Application and F...

Application and Function Areas - artificial intelligence: Individual applications and function often drive "AI" research much more than the long term relative field described

Illustrate some notations of object modeling notations, Illustrate some not...

Illustrate some notations of object modeling notations A classifier is a mechanism which describes behavioural and structural features. In UML significant classifiers are cla

Give an example of resource allocation graph & deadlocked, Suppose there ar...

Suppose there are 2 copies of resource A, 3 copies of resource B, and 3 copies of resource C. Suppose further that process 1 holds one unit of resources B and C and is waiting for

#project, how to build PVR set-top box using raspberry

how to build PVR set-top box using raspberry

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd