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Consider that a list of record or a table is stored in the memory and you wish to find some information in that particular list. E.g. the list comprises three fields as displayed below:
Assume that we want to find the age and ID number of Ravi. If we use conventional RAM, it is essential to give the exact physical address of entry associated to Ravi in the instruction access entry such as:
READ ROW 3
Another alternative idea is that we explore the whole list by means of the Name field as an address in instruction like:
READ NAME = RAVI
Again with serial access memory this option may be implemented simply but it's a very slow process. An associative memory assists at this point and concurrently examines all the entries in the list and returns the desired list very rapidly. SIMD array computers have been developed with associative memory. This memory is content addressable memory by which it's meant that multiple memory words are accessible concurrently. The parallel accessing feature support parallel search and parallel compare too. This ability can be used in numerous applications like:
The inherent parallelism characteristic of this memory has huge advantages and impact in parallel computer architecture. The associative memory is expensive compared to RAM. The array processor built with associative memory is termed as Associative array processor. In this section we explain a number of categories of associative array processor. Kinds of associative processors are based on organisation of associative memory. So first we discuss about associative memory organisation.
diagrams of picket fence problem
Q. Explain about Open System? The 'Open System' is a system within its environment. It receives input from environment as well as provides output to environment. Illustrati
Hello there i have 4 exams of ICT and i am after a tutor who can help me in those 4 subjects. One hour for each subjects will be good for me as i have sample papers ready for all s
What is dynamic random access memory Computer memory today comprises mainly of dynamic random access memory (DRAM) chips which have been built into multi-chip modules that are
real world applications
A vertical flashing line that permits the user where text will be inserted.
Explain the relationship amongst Translated address and Linked address. Translated address: Address assigned through the translator Linked address: Address assigned
In a raw Itanium, a "Processor Abstraction Layer" (PAL) is integrated into the system. When it is booted the PAL is loaded into the CPU and gives a low-level interface that abstrac
The FontMetrics class is used to describe implementation-specific properties, like ascent and descent, of a Font object.
Q. What is Block size of cache memory? Block Size: Block size means unit of data (few memory words) exchanged between main and cache memory. As block size increases from very
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