Advantage to depth first search, Computer Engineering

Assignment Help:

Advantage to depth first search:

It just looks like it will be a long period it finds 'DAN' until. This highlights an important drawback for depth first search. It can regularly go deep down paths for which we have no solutions, when there may be we get any solution much higher ups the tree, although on a different branch. Also, depth for first search is not, in generally, may be complete. 

Rather than basically adding the next agenda item directly needs to the top of the agenda, it might be a superior idea to make sure that every node in the tree is fully expanded before moving on to the next depth in the search. This is other kind of depth first search which the Russell and Norvig explain in their rules and regulation. For our DNA example we see that, if we did this, the search tree would like this: 

And the big advantage to depth first search is just that it requires very much less memory to operate and control than breadth first search. If we just count the number of 'alive' nodes in the figure above, it amounts to only 4, just because the ones on them in the bottom row are not to be expanded due to the depth edge. However, it can be shown that if there an agent wants to search for all solutions then up to a depth of d in a space with branching factor b, and in a depth first search its only needs to remember up to a more maximum of b*d states at any one time easily. 

To put this in the perspective, if there our professor wanted to search for all names up to length 8, she would only have to remember that 3 * 8 = 24 for different strings to complete the procedure a depth first search is rather than 2187 in a breadth first search.


Related Discussions:- Advantage to depth first search

What are single stage and multistage networks, What are single stage and mu...

What are single stage and multistage networks? Compare the strengths and weaknesses of each. OR List the major difference in single stage, two stages and three stage Netw

What is a spool request, What is a Spool request? Spool requests are f...

What is a Spool request? Spool requests are formed during dialog or background processing and placed in the spool database with information about the printer and print format.

Data phases - computer architecture, Data phases: After the address ph...

Data phases: After the address phase (particularly, starting with the cycle that DEVSEL# goes low) comes a burst of one or more data phases. In all the cases, initiator drives

What is time multiplexed space switching, What is time multiplexed space sw...

What is time multiplexed space switching? Explain w ith a neat diagram. Time division switches, an inlet or an outlet corresponded to a particular subscriber line with one s

Explain the resolution of an ADC, Explain the Resolution of an ADC. ...

Explain the Resolution of an ADC. Ans. Resolution- It  is  the  smallest  possible  change  in  input  voltage  the same as  the  fraction  of percentage of the full s

Define miss rate, Define miss rate? It is the number of misses' states ...

Define miss rate? It is the number of misses' states as a fraction of attempted accesses.

Design a logic circuit, Ask questDesign a logic circuit with 4 inputs A, B,...

Ask questDesign a logic circuit with 4 inputs A, B, C & D that will produce output ‘1’ only whenever two adjacent input variables are 1’s. A & D are also to be treated as adjacent,

Explian two limitations of dead-box analysis, (a) Explian two limitations o...

(a) Explian two limitations of dead-box analysis. (b) Describe why memory analysis is difficult. (c) With reference to the "Shadow Walker" rootkit, explain what is meant by

What is algorithm design technique, What is Algorithm Design Technique? ...

What is Algorithm Design Technique? An  algorithm  design  method  is  a  general  approach  to  solving  problems  algorithmically  that  is applicable to a variety of proble

How do we synthesize verilog into gates with synopsys, How do we synthesize...

How do we synthesize Verilog into gates with Synopsys?  The answer can, of course, occupy various lifetimes to completely answer.. BUT.. a straight-forward Verilog module can b

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd