Address translation - computer architecture, Computer Engineering

Assignment Help:

Address translation:

  • Compiler time: If it is known in advance that a program will reside at a particular location of primary memory, and then the compiler can be told to make the object code with complete addresses right away. For instance, the boot sect in a bootable disk can be compiled with the starting point of code set to 007C:0000.
  • Load time: It is very rare that we already know the location a program will be assigned ahead of its execution. In mostly cases, the compiler has to generate reloadable code with logical addresses. Therefore the address translation can be performed on the code at the load time. Above figure shows that a program is loaded at location x. If the complete program resides on a monolithic block, then every memory reference can be translated to be physical by added to x.

898_Address translation.png

               An Example of fixed partitioning of a 64-Megabyte memory

 

 

 


Related Discussions:- Address translation - computer architecture

Java Applet, Simple codes for robot using applet

Simple codes for robot using applet

Define the most common biometrics, What is most common biometrics? Explain ...

What is most common biometrics? Explain in brief. The most common biometrics is as given below: Face geometry (Photo): The computer captures the picture of your face and m

What is sector sparing, What is sector sparing? Low-level formatting al...

What is sector sparing? Low-level formatting also sets aside spare sectors not visible to the operating system. The controller can be told to change each bad sector logically w

Dynamic address translation - computer architecture, Dynamic address transl...

Dynamic address translation :  If, when executing an instruction, a CPU fetches an instruction located at a specific virtual address, or fetches data from a particular virtual

Target - data phase, Target abort -computer architecture: Usually, a t...

Target abort -computer architecture: Usually, a target holds DEVSEL# asserted through the final data phase. However, if a target desserts DEVSEL# before disconnecting without

Describe data parallel model, Describe Data Parallel Model? In data par...

Describe Data Parallel Model? In data parallel model most of parallel work concentrates on performing operations on a data set. Data set is characteristically organised in a co

Describe the term- system analyst design, Describe the term- System analyst...

Describe the term- System analyst Design Once analysis has taken place and systems analyst has some idea of the scale of problem and what needs to be done, subsequent stage is

For which class address 192.5.48.3 belogs, Address 192.5.48.3 belongs to? ...

Address 192.5.48.3 belongs to? Address 192.5.48.3 belongs to class C.

Era of first generation computers, Q. Era of first generation computers? ...

Q. Era of first generation computers? The trends that were encountered at the time of the era of first generation computers were: Centralized control in a single CPU (al

Explain wait for graph-resource request and allocation graph, Explain Wait ...

Explain Wait for graph (WFG) with Resource request and allocation graph (RRAG). WFG with RRAG: A graph G = (V,E) is termed as bipartite if V can be decomposed in two

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd