Address phase - computer architecture, Computer Engineering

Assignment Help:

Address phase:

A PCI bus transaction starts having an address phase. The initiator,  after seeing that it has GNT# and the bus is inactive, drives the target address onto the AD[31:0] lines, the associated command (for example: I/O write or memory read,) on the C/BE[3:0]# lines, and pulls FRAME# low.

Each other device inspect the address and command & decides whether to respond as the target by asserting DEVSEL#. Device has to respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within one or two cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (In fact, the time to respond is 2.5 cycles, since PCI devices have to transmit all signals half a cycle early so that they can be retaining3 cycles later.)Note that a device have to latch the address on the first cycle; the initiator is needed to remove the address and command from the bus on the following cycle, even before retaining a DEVSEL# response. The extra time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is permitted for some address ranges. It is generally used by an ISA bus bridge for addresses within its particular range (16 bits for I/O and 24 bits for memory).

On the sixth cycle, if there has been no response, the initiator can abort the transaction by deserting FRAME#. It is known as master abort termination and it is customary for PCI bus bridges to return all- ones data (0xFFFFFFFF) in this particular case. PCI devices therefore are generally designed to ignore by using the all-ones value in essential status registers, so that such type of error may be easily detected by software.

 


Related Discussions:- Address phase - computer architecture

Why wap gateways are used, Why WAP gateways are used? The Wireless Appl...

Why WAP gateways are used? The Wireless Application Protocol Gateway is a very unique product giving semi -automatic redirection of HTML documents to WAP compatible mobile phon

Determine flip flop the msi chip is dual edge triggered, The MSI chip 7474 ...

The MSI chip 7474 is ? Ans. MSI chip 7474 is TTL, dual edge triggered D Flip-Flop.

Explain erasable programmable rom (eprom) - computer memory, Explain Erasab...

Explain Erasable Programmable ROM (EPROM) - Computer Memory? An EPROM is a ROM that can be reprogrammed and erased. A little glass window is installed at the top of the ROM pac

Data routing functions-network properties, Data Routing Functions The d...

Data Routing Functions The data routing functions are the functions which when implemented  the path among the source and the objective. In dynamic interconnection networks the

Differentiate b/w program translation and interpretation, Differentiate bet...

Differentiate between program translation and program interpretation. The program translation model makes the execution gap through translating a program written in a program

Flynn’s classification, Flynn's Classification Flynn's classification i...

Flynn's Classification Flynn's classification is based on multiplicity of data streams and instruction streams observed by the CPU during program execution. Let Ds and Is  are

Example of shared programming using library routines, Q. Example of shared ...

Q. Example of shared programming using library routines? Think about subsequent set of statements  Process A                                  Process B                  :

How is a property designated as read-only, How is a property designated as ...

How is a property designated as read-only?  In VB.NET: Public Read-Only Property Property Name As Return Type Get? Your Property execution goes in here End Get End Property.

Mention the various IC logic families, Mention the various IC logic familie...

Mention the various IC logic families. Ans. Different  IC Logic Families: Digital IC's are fabricated through employing either the Unipolar or the Bipolar Technologies and are te

Critical capabilities for superior firm performance, What are the critical ...

What are the critical capabilities for superior firm performance in e-commerce? Three firm capabilities which are critical for superior firm performance within e-commerce are:

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd