8251 Programmable/Communication Interface

As an instance of a serial interface device let us suppose Intel's 8251 A programmable communication interfaces. The 8251A is diagrammed in given figure. It is capable of being programmed for synchronous / asynchronous communication.  The data that is in buffer and data-out buffer registers share the similar port address. For input, the serial bit stream is arriving on the R x D pin is shifted into the receiver shift register and then the data bits are transferred to the data-in buffer register, where they might be input by the CPU. On the other hand on output the data bits put in the data-out buffer register by the CPU are transferred to the transmitter shift register and, along with the essential synchronization bits, are shifted out through the T x D pin. Among other things the contents of the mode register, which are begin by the executing program, determine whether the 8251A is in synchronous mode or asynchronous mode and the format of the characters being received and transmitted. The control register, which is set by the program, controls the operation of the interface, and the status register makes sure information available to the executing program. Obviously, the sync character registers are for storing the sync characters required for synchronous communication.

Even though all 7 of the registers on the left side of Figure 4.7 may be accessed by the processor, the 8251A is associated with only 2 port addresses. The C/D pin is linked to the address line AO and AO differentiates the 2 port addresses. The 8251A internally interprets the C/D, RD, and WR signals as follows: