8237 modes-microprocessor, Assembly Language

Assignment Help:

8237 modes :

Intel 8237 can be set to four different type of style of transfer:

1) Single - One transfer at a time,  it allow processor access to the bus between transfers.

2) Block - Transfer all data, it do not allow processor access to the bus (may cause problems with memory refresh).

3) Demand - it keep transferring as long as target keeps DRQ asserted.

4) Cascade - it allow a slave controller use of the DMAC (used for DRQ4).

 

(A) In addition, the DMA controller can be set to make continuous transfers

o   It known as auto-initialized DMA

o   normally DMA is known as "single-cycle"

 

(B) 8237 is clocked at 1/2 of ISA Bus (0.5 *BLCK)

o   up to 4.166MHz (8.33 Mhz ISA)

o   Maximum transfer rate: 4.166MB/s (16-bit DMA)

o   Maximum Programmed I/O transfer rate: 2.77 MB/s

 

(C) Size of transfer

o   Master can only produce word-sized transfers

o   Slave can produce byte-sized transfers

o   Minimum transfer size: 1 byte

o   Maximum transfer size: 64KB (8-bit),128KB (16-bit)

 


Related Discussions:- 8237 modes-microprocessor

8086 assembly language program, move a byte string ,16 bytes long from the ...

move a byte string ,16 bytes long from the offset 0200H to 0300H in the segment 7000H

8086 assembly language, write and run a programme using 8086 assembly langu...

write and run a programme using 8086 assembly language that interchange the lower four bits of AL registered with upper four bits.

Program to convert decimal to binary number, Program is written but has err...

Program is written but has errors returning values from the procedure.

Timing diagram of minimum mode, give the explaination of timing diagram min...

give the explaination of timing diagram minimum mode memory write cycle

Dec-arithmetic instruction-microprocessor, DEC:  Decrement :- The decremen...

DEC:  Decrement :- The decrement instruction subtracts 1 from the contents of the particular memory location or register. All the conditions code flags except carry flag are affec

Cache controller-microprocessor, Cache controller The cache controller ...

Cache controller The cache controller is the mind of the cache.  Its responsibilities include:  performing the  snarfs and snoops, updating the  TRAM  and SRAM and implementing

Project ideas, can u please give me ideas on Assembly Language Projects usi...

can u please give me ideas on Assembly Language Projects using Nasm

Stand alone system - assembly language program, Develop an assembly languag...

Develop an assembly language program for the system and simulate it using MPLAB. From this produce a demo program (in Assembly language) that will run on the MatrixMultimedia Devel

Adc-arithmetic instruction-microprocessor, ADC: Add with Carry:- This instr...

ADC: Add with Carry:- This instruction performs the similar operation a like ADD instruction, but adds the carry flag bit (which might be set as a result of the previous calculatio

Ocw-microprocessor, There are 3 kinds of OCWs. The command word OCWI is u...

There are 3 kinds of OCWs. The command word OCWI is utilized for masking the interrupt requests; when the mask bit corresponding to an interrupt request is value 1, then the requ

Write Your Message!

Captcha
Free Assignment Quote

Assured A++ Grade

Get guaranteed satisfaction & time on delivery in every assignment order you paid with us! We ensure premium quality solution document along with free turntin report!

All rights reserved! Copyrights ©2019-2020 ExpertsMind IT Educational Pvt Ltd