For an 8088 the 2 addresses linked with an 8259A are normally consecutive, and the AO line is associated to the AO pin, but because there are just 8 data pins on the 8259A and the 8086 always inputs the interrupt pointer from the lower 8 bits of its 16-bit data bus, all data transfers to and from the 8259A might be made over the lower byte of the bus. The simplest way to guarantee that all transfers will utilize the lower half of the bus is to attach the Al line to AO and utilize two consecutive even addresses, with the first being divisible by four. However, to simplify the discussion, the second address will be referred to as the odd address for both cases.
The control portion of the 8259A contains several programmable bits that can be viewed as being contained in seven 8-bit registers. These group containing the operation command words (OCWs). The starting command words are usually set by an beginner routine when the computer system is first brought up and remain constant throughout its whole operation. Contrastively, the operation command words are utilized to dynamically control the processing of interrupts.
The IRR (and its linked masking logic), and priority resolver, are for controlling and receiving the interrupts that arrive at the pins IR7-IRO. The IRR latches the incoming requests and, in conjunction having the priority resolver, let unmasked requests with enough priority to put a one on the INT pin. The priority resolver logic determines the priorities of the requests in the IRR and the ISR is used for holding the requests currently being processed.
After a bit in the IRR is set to one it is compared with the equivalent mask bit in the IMR. If the mask bit value is set zero the request is passed on to the priority resolver, but if the value is 1, the request is blocked. When an interrupt request is input to the priority resolver its priority is checked and, if according to the current state of the priority resolver the interrupt is to be sent to the CPU and the INT line is activated.
Supposing that the IF flag in the CPU is 1, the CPU will go to its interrupt sequence at the completion of the current instruction and return 2 negative pulses on the INTA line. On the arrival of the first pulse, the IRR latches are disabled so that the IRR will avoid further signals on the IR7-IRO lines. This state is maintained till the end of the second INTA pulse. The first INTA pulse will also cause the suitable ISR bit to be set and the corresponding IRR bit to be cleared. The 2nd INTA pulse make the current contents of ICW2 to be placed on the D7-DO, and the CPU utilize this byte as the interrupt type. If the automatic end of interrupt (AEOI) bit in ICW4 value is set one, at the end of the second INTA pulse the ISR bit that was set by the first INTA pulse is cleared; or else the ISR bit is not cleared till the accurate end of interrupt (EOI) command is sent to OCW2.
As show above, the initialization command words are usually filled by an initializing routine when the system is turned on and have the control bits that are held constant throughout the system's operation. The 8259A has an even address (AO = 0) and an odd address (AO = 1) linked with it and the initialization command words might be filled consecutively using the even address for ICWI and the odd address for the remaining ICWs.