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a. Sketch the excitation diagram indicating the last states and next states.
b. Build the circuit using a Synchronous Counter with JK FF and NAND gates only. Replicate the circuit and prove that it is working using Multisim. You are needed to obtain a printscreen of your circuit. There should be a total of 5 screen captures, every describing one state. Attach softcopy of multisim simulation file in this assignment.
c. Sketch the Timing Diagram depicting the outputs from the Synchronous Counter relative to the CLOCK.
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can you deign the schematic of a modified digital clock at the gate as well as the IC level and then construct the circuit, lab spec and industral spec?
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