Writre an abel or vhdl program for a sticky-counter state

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Reference no: EM13286975

writre an ABEL or VHDL program for a "sticky-counter" state machine with eight states, S0-S7, that are coded into 3 bits in binary counting order. Besides CLOCK, the machine should have 2 inputs, RESET and ENABLE, and one output, DONE. The machine should go to state S0 whenever RESET is asserted. When RESET is negated, it should mov e to next-numbered state only if ENABLE is asserted. However, once it reaches state S7, it should stay there unless RESET is again asserted. The DONE output should be 1 if only the machine is in state S7 and ENABLE is asserted.

Reference no: EM13286975

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