Reference no: EM133424235

Part A: THE CPU AND MEMORY (Chapter 7)

If the memory register for a particular computer is 32 bits wide, how much memory can this computer support?
Show the steps of the CPU fetch-execute cycle (micro operations) for the following instructions in the Little Man instruction set:
SUBTRACT,
IN,
COFFEE BREAK,
BRANCH ON CONDITION
Show the steps of the CPU fetch-execute cycle (micro operations) for an instruction that produces the 2's complement of the number in accumulator A (calculator). (8 marks)
Assume that SP is the stack pointer regiester, a special purpose register that always refers to the top of the stack. PUSH is an instruction that pushes the address of the next instruction into the top of the stack. Show the steps of the CPU fetch-execute cycle (micro operations) for the PUSH instruction.

Part B: CPU AND MEMORY: DESIGN, ENHANCEMENT, AND IMPLEMENTATION (Chapter 8)

Consider a CPU that implements a single instruction fetch-decode-execute-write- back pipeline for scalar processing. The execution unit of this pipeline assumes that the execution stage requires one step. Describe, and show in diagram form, what happens when an instruction that requires one execution step follows one that requires four execution steps.
Some systems use a branch prediction method known as static branch prediction, so called because the prediction is made on the basis of the instruction, without regard to history. One possible scenario would have the system predict that all conditional backward branches are taken and all forward conditional branches are not taken. Recall your experience with programming in the Little Man Computer language. Would this algorithm be effective? Why or why not? What aspects of normal programming, in any programming language, support your conclusion?
Suppose we are trying to determine the speed of a computer that executes the Little Man instruction set. The LOAD and STORE instructions each make up about 25% of the instructions in a typical program; ADD, SUBTRACT, IN, and OUT take 10% each. The various branches each take about 5%. The HALT instruction is almost never used (a maximum of once each program, of course!).
Determine the average number of instructions executed each second if the clock ticks at 100 MHz.
Now suppose that the CPU is pipelined, so that each instruction is fetched while another instruction is executing. (You may also neglect the time required to refill the pipeline during branches and at the start of program execution.) What is the average number of instructions that can be executed each second with the same clock in this case?
Consider a cache memory that provides three hundred 16-byte blocks. Now consider that you are processing all the data in a two-dimensional array of, say, four hundred rows by four hundred columns, using a pair of nested loops. Assume that the program stores the array column by column. You can write your program to nest the loops in either direction, that is, process row by row or column by column. Explain which way you would choose to process the data? Why?