Write vhdl for d flip-flop with synchronous active-low clear

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Reference no: EM13248453

Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset, and responsive to a rising edge clock. Use D for the input, Q for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.

Reference no: EM13248453

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