Write vhdl code to implement the following state table

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Write VHDL code to implement the following state table. Use two processes. State changes should occur on the falling edge of the clock. Implement the Z1 and Z2 outputs using concurrent conditional statements. Assume that the combinational part of the sequential circuit has a propagation delay of 10 ns, and the propagation delay between the rising-edge of the clock and the state register output is 5 ns.

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Reference no: EM131368281

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