Reference no: EM132416202

Questions -

1. Draw the Block Diagram, VHDL code and truth table for the following using process and if statements.

a. OR Gate

b. 2 Input Comparator

c. 1 of 4 decoder

d. 2 bit adder

e. JK Flip flops

2. The following VHDL code fragment contains erroneous syntax. Re-write the code in its corrected format .Draw the block diagram and truth table. Describe the operation of the circuit described by the code.

3. Identify and write the correct code. Identify and draw table for the circuit.

4. Write the vhdl code for RS FF.

5. Design a 2-bit Gray counter.

6. Draw the state table and determine the logic equations for the inputs of JK flip-flops using Karnaugh maps.

i) Draw the full schematic diagram of the circuit obtained at point i).

ii) Determine the logic equation for the output Y of this FSM.

iii) Add the circuit required to implement this output to the main diagram derived at point ii).

a. Use JK Flip flop

b. Use JK Flip flop

7. Using the 32k x 4 ROM in the figure, create a 64k x 8 ROM.

8. Using the 32k x 4 ROM in the figure, create a 96k x 8 ROM.

9. Using the 32k x 4 ROM in the figure, create a 128k x 4 ROM.

10. Theory Focus Areas

i. Variable vs signal in vhdl

ii. PAL vs GAL

iii. Von-Neuman and Harvard architectures

iv. Building blocks of testbench

v. std_logic and std_logic_vector

vi. VHDL design vs VHDL testbench

vii. VHDL and applications

11. The Boolean functions of a 4-input logic circuit are given as follows:

A(W,X,Y,Z) = Σm(0,2,4,6,8,10,11)

B(W,X,Y,Z) = Σm(0,3,5,7,9,10,11,15)

C(W,X,Y,Z) = Σm(1,6,10,12,14)

D(W,X,Y,Z) = Σm(3,4,5,8,9,10,12)

E(W,X,Y,Z) = Σm(7,9,10,11,13)

F(W,X,Y,Z) = Σm(1,2,6,7,8,10,11)

12. The Boolean functions of a 4-input logic circuit are given as follows:

A(W,X,Y,Z) = Σm(1,4,7,8,10,11)

B(W,X,Y,Z) = Σm(0,3,6,7,9,13,15)

C(W,X,Y,Z) = Σm(0,7,10,11,14)

D(W,X,Y,Z) = Σm(2,4,6,8,9)

E(W,X,Y,Z) = Σm(1,4,10,12,13,14)

Note - All figures and required information in attached file.

Attachment:- Assignment File.rar