Reference no: EM131277786
Write ABEL test vectors or a VHDL or Ve1ilog test bench to check for proper operation of the state machine you designed in D1ill 7 .34.
D1ill 7 .34
Write an ABEL, VHDL, or Verilog program for a state machine that is similar to the one specified in Drill 7 .32 except that when enabled, it counts "two steps forward, one step back." The machine should have one additional output, BACK, that is asserted if ENABLE is asserted and the machine is going to count back on the next clock edge. Once the machine gets to state S7, it never counts back. Comment your program to describe your strategy for creating thi behavior and how many additional state bits are needed.
Drill 7 .32
Write an ABEL, VHDL, or Verilog program for a "sticky-counter" state machine with eight states, SO-S7, that are coded into three bits in binary counting order. Besides CLOCK, your machine should have two inputs, RESET and ENABLE, and one output, DONE. The machne should go to state SD whenever RESET is asserted. When RESET is negated, it should move to next-numbered state only if ENABLE is asserted. However, once it reaches state S7, it should stay there unless RESET is again asserted. The DONE output should be l if and only if the machine is in state S7 and ENABLE is asserted.
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: The machne should go to state SD whenever RESET is asserted. When RESET is negated, it should move to next-numbered state only if ENABLE is asserted. However, once it reaches state S7, it should stay there unless RESET is again asserted. The DONE ..
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