Write a vhdl testbench to verify your design

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Reference no: EM131233796

Computer Assignment 3 Synthesis of Combination Circuits Division by Constant

Consider an unsigned integer division by constant circuit that accepts an input of 8 bit wide and divides it by constant value 21.

The divider circuit should output two values as remainder and quotient. As you know the division operator is not synthesizable! As an example if input is 109, the remainder is 5 and quotient is 4 while if input is 20, remainder is 20 and quotient is 0.

Design a synthesizable integer division by 21 circuit that performs the above operation. Design your circuit for minimum area.

This means that you need to decide what is the minimum proper number of bits needed for each of the intermediate signals and outputs.

Hint: Use the repeated subtraction method to synthesize this circuit. 1. Draw a block diagram of the complete design that implements your algorithm. 2. Write a VHDL code to model this division by constant circuit. 3. Write a VHDL testbench to verify your design.

Present a test vector that verifies the functionality of the design for all critical cases.

Reference no: EM131233796

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