Reference no: EM132017848

The objective of this lab is to practice your Verilog coding and the modeling of combinational logic.

Lab Goal:

For this lab, you will write the Verilog code for a 4-bit arithmetic/logic unit (ALU) according to the specifications outlined under the specifications section of this document. You will write a TestBench to thoroughly test your design and you will program the BASYS3 board in order to implement your design.

Design Specifications for the ALU

The VERILOG model you implement should be for a 4-bit arithmetic/logic unit (ALU) which has as inputs two 4-bit vectors aluin_a and aluin_b as well as a carry in, Cin. The output is a 4-bit vector alu_out. The ALU should operate on the inputs depending on the control inputs C in the following table:

C(3 down to 0)	Operation
0 0 0 0	alu_out = aluin_a + aluin_b
0 0 0 1	alu_out = aluin_a + aluin_b + Cin
0 0 1 0	alu_out = aluin_a - aluin_b
0 0 1 1	alu_out = aluin_a - aluin_b - Cin
0 1 0 0	alu_out = aluin_a logical shifted right by aluin_b
0 1 0 1	alu_out = aluin_a arithmetic shifted right by aluin_b
0 1 1 0	alu_out = aluin_a rotated right by aluin_b
0 1 1 1	alu_out = all 0's
1 0 0 0	alu_out = aluin_a OR aluin_b (bitwise or)
1 0 0 1	alu_out = aluin_a AND aluin_b (bitwise and)
1 0 1 0	alu_out = aluin_a XOR aluin_b (bitwise xor)
1 0 1 1	alu_out = NOT aluin_a (bitwise inversion)
1 1 0 0	alu_out = undefined. But in this mode, all 16 LEDs should be used to display the 1st and 2nd character of your last name (again)
1 1 0 1	alu_out = You decide and tell me what you chose to implement
1 1 1 0	alu_out = aluin_a logical shifted left by aluin_b
1 1 1 1	alu_out = aluin_a rotated left by aluin_b

Other Design Requirements

1. If a carry out is generated, then a signal Cout should be set.

2. If the result is all 0's, then a signal zero should be set.

3. The test bench should test every operation as well as the Cout and Cin for correct operation. Meaning that the test bench should give the inputs such that you can verify all the test cases.

Signal to BASYS3 Hardware Mapping

The signals you use should map to the following BASYS3 I/Os as per the following table:

aluin_a[3:0]	SW3, SW2, SW1, SW0
aluin_b[3:0]	SW7, SW6, SW5, SW4
C[3:0]	SW15, SW14, SW13, SW12
Cin	BTNC
alu_out[3:0]	LD3, LD2, LD1, LD0
Cout	LD14
zero	LD15
Special Case when C=1100, First two characters of your last name in ASCII.	All 16 LEDs like in Lab 1

Design Suggestions

1. Your design should have a top-level module which is the ALU.

2. Inside the top-level, you should instantiate a 4-bit adder which in turn instantiates 1-bit adder modules. Inputs to the 4-bit adder module can be multiplexed (using, for example, a CASE statement) to do shifting, rotation, logic operations. etc.)

3. 4-bit subtraction can be implemented by taking the 2's compliment of aluin_b prior to presenting it as an input to the adder module.

Submission of Completed Lab:
Upon completing this lab, you must upload to blackboard the following files:
ALU.v ← The file containing the ALU module and any additional modules you have instantiated into it. ALU_tb.v ← The file containing your testbench file
ALU.bit ← The bitstream file for programming the BASYS3 board. A report document uploaded as a .pdf file showing

1. Example waveforms (a screen capture) containing aluin_a, aluin_b, C, Cin, Cout, alu_out and zero when tested by your testbench for any one of the C conditions in Table 1 (except C=1100). Make sure the signals are clear and the signal values are legible. Put in figure captions explaining what the figure shows.

2. An explanation of what you chose to implement when input C is 1101

3. Your argument and code examples as to why you believe your testbench exhaustively tests your design.