Reference no: EM132694499
Part 1. Choose the best answer
( ) 1. Duty cycle is defined to be the percentage of time within a period that the waveform is high. Assume that the TIM5->ARR holds 1000 and the TIM5->CCR4 holds 600. What is the duty cycle of the TIM5_CH4 pin output? (a) 60% (b) 50% (c) 40% (d) 80
( ) 2. Suppose a timer is counting with a 10 MHz clock, what is the timer count to create a time delay of 7 ms? (a) 10,000 (b) 70,000 (c) 30,000 (d) 7,000
( ) 3. What instruction can put the ARM processor in sleep mode and needs an interrupt to wake up the processor? (a) WFI (b) WFE (c) CPSIE I (d) CPSID I
( ) 4. In the SPI interface, how to send out a frame? (a) write the data frame into the SPIx->DR register (b) read from the SPIx->DR register (c) write the data frame into the SPIx->CRI register (d) write the data frame into the SPIx->CR2 register
( ) 5. For the MCP4922 DAC, if the gain is set to 1 and the reference voltage is set to 5 V, what value (the lower 12 bits to be sent) can generate 3 V output? (a) 2000 (b) 1000 (c) 1457 (d) 2457
( ) 6. Suppose the frequency of the clock input is 80 MHz and you write 7, 1000 into the TIM2->PSC, TIM2->ARR register and also select center-aligned PWM mode 1, what is the resultant frequency of the PWM waveform? (a) 10-KHz (b) 5-kHz (c) 2-KHz (d) 1- KHz
( ) 7. An interrupt which is preempted is (a) inactive (b) pending (c) active (d) reset
( ) 8. For exception tail-chaining to occur, which of the following must exist? (a) no pending interrupt (b) there is a preempted interrupt (c) there is a pending interrupt with enough priority (d) there are pending interrupts that do not have enough priority
( ) 9. IF the output compare match for TIM5 channel 4 occurred, the which of the following flag in the TIM5->SR register will be set? (a) UIF (b) CC4IF (c) CC4OF (d) TIF
( ) 10. Which of the following modes is best for measuring the period and pulse width of a signal? (a) PWM mode 1 (b) PWM mode 2 (c) input capture (d) PWM input mode
1. Write a C function to configure PD4 pin to interrupt the CPU on the falling edge and also enable the interrupt. Fill in the appropriate statements between { and }. Solution: void initPB2lnterrupt (void) {}