Which cache design is better for each of these benchmarks

Assignment Help Basic Computer Science

Reference no: EM131318748

1. Which cache design is better for each of these benchmarks? Use data to support your conclusion.

2. Shared cache latency increases with the CMP size. Choose the best design if the shared cache latency doubles. Off -chip bandwidth becomes the bottleneck as the number of CMP cores increases. Choose the best design if off -chip memory latency doubles.

Reference no: EM131318748

Questions Cloud

Calculate the cpi again this time using a virtualized system : Calculate the CPI again, this time using a virtualized system. How do these CPIs change if the system has half the I/O accesses? Explain why I/O bound applications have a smaller impact from virtualization.

Contrast the ideas of virtual memory and virtual machines : Compare and contrast the ideas of virtual memory and virtual machines. How do the goals of each compare? What are the pros and cons of each? List a few cases where virtual memory is desired, and a few cases where virtual machines are desired.

Design a finite state machine to enable use of write buffer : What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer?

List the possible values of c and d for an implementation : For various combinations of write policies and write allocation policies, which combinations make the protocol implementation simpler?

Which cache design is better for each of these benchmarks : Shared cache latency increases with the CMP size. Choose the best design if the shared cache latency doubles. Off -chip bandwidth becomes the bottleneck as the number of CMP cores increases. Choose the best design if off -chip memory latency doubl..

How much improvement can be achieved over private l2 : Discuss the pros and cons of shared vs. private L2 caches for both single-threaded, multi-threaded, and multi programmed workloads, and reconsider them if having on-chip L3 caches.

How much more off -chip memory bandwidth is needed : Assume new generations of processors double the number of cores every 18 months. To maintain the same level of per-core performance, how much more off -chip memory bandwidth is needed for a processor released in three years?

Show your structure definition code : Which fields in a log entry will be accessed for the given log processing function? Assuming 64-byte cache blocks and no prefetching, how many cache misses per entry does the given function incur on average?

Identify the loop-carried dependences in the above code : Identify the loop-carried dependences in the above code. Identify the dependent program variable and assembly-level registers. You can ignore the loop induction variable j.

User Account

All Pages