Where each instruction is bits wide

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Reference no: EM13234582

A DMA module is transferring characters to main memory from an external device transmitting at 500,000 bits per second (bps). The processor can fetch instructions at the rate of 1 million instructions per second where each instruction is 64 bits wide. Assume the bus used to access main memory is 64 bits wide and that the DMA module has priority over the CPU for memory access. In other words, when the DMA module wants to access memory, the CPU must pause for a cycle until the DMA module is done. a) How many bus cycles per second will be used by the DMA module? b) By how much (percentage) will the processor be slowed down due to the DMA activity? c) In a system without DMA, an interrupt would be generated each time 64 bits of data were available for transfer from the external device. For each interrupt, the processor would need to fetch a 100-instruction interrupt handler routine from memory, then transfer the data from the external device into a register, and finally store the data into main memory. How many bus cycles per second are used to handle the data stream now? d) By how much will the processor be slowed down?

Reference no: EM13234582

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