Reference no: EM133325256

Assignment: De?nition and Background: To access data from a typical DRAM, we need to activate the row to bring content into row buffer; then select the column from the row butter. If the next access to the bank is to a different row, we need to close the row with precharge, then open the new row with activation. If the next access is to the same row. there is no need to do the activation step. just select column from the row buffer and do the read or write operation. Open-page policy: we do not issue precharge to close the row right after the access Close-page policy: we always close a row right after an access Assumptions: Assuming that we have the row buffer size as BKB. Every read or write to DRAM is of size 643. Assuming it takes 5 cycles to precharge, 5 cycles to activate, and 4 cycles to read a column from the row buffer. The time to send 643 data on the bus is 8 cycles.

Question: 1. Under open-page policy, what would be the number of cycles needed to read a cacheline when it is a row buffer hit? How about a row buffer miss?

Question: 2. Under close-page policy, what would be the number 0! cycles needed to read a cacheline when it is a row buffer hit? How about a row buffer miss?

Question: 3. What would be the minimum row buffer hit rate for you to choose open-page policy over close-page policy? Assume that every access to DRAM is separated by enough time to ?nish a random new access.