What reductions in maximum operating frequency

Reference no: EM131019466

A logic-circuit family with zero static power dissipation normally operates at VDD =2.5 V. To reduce its dynamic power dissipation, operation at 1.8 V is considered. It is found, however, that the currents available to charge and discharge load apacitances also decrease. If current is (a) proportional to VDD or (b) proportional t V2 DD, what reductions in maximum operating frequency do you expect in each case?

Reference no: EM131019466

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