What problem does this pose for subroutine return

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Reference no: EM131942676

Problem

In the pipelined version of SRC, the branch instructions have a branch delay slot to avoid stalling the pipeline for a cycle. Assume that the compiler schedules instructions into the branch-delay slot. In this context, consider the implications of the brl instructions scoring PC = 4 in the link register.

a. What problem does this pose for subroutine return?

b. How should the compiler handle this problem?

Reference no: EM131942676

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