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1) Given the following set of inputs, x[n], to a three-term moving average filter, calculate y[n] for the last output where all the inputs to the moving average are defined.
x[0] = 3, x[1] = 5, x[2] = 8, x[3] = 7, x[4] = 4, x[5] = 2, x[6] = 1
2) What is the value of the coefficient +0.1837 if it is quantized to 10 bits?
3) What is the main reason that bilinear transformation is used in IIR filter design?
How much power is delivered from dependent source? How much power is lost in the output resistance?
In the Doherty amplifier of Fig. 12.67(a), the value of a is chosen equal to 0.5. Plot the waveforms at x = 0 and x = ?/4, assuming Z0 = RL.
Obtain a minimized equation for the function F(X,Y,Z)=Σ(0,1,3) + Σmd(5,6,7) then draw a schematic to implement the minimized function in SOP form using AND, OR and inverters. Draw a schematic implementing the function using only NOR and inverters.
Repeat for rate 3/4 BCH codes having block length n = 15, 31, 63, and 127. What conclusions can you draw from this exercise?
Obtain the Nyquist plot for the open-loop transfer function given by Eq. Show all the stability margins on your plot.
The FM input to a PLL demodulator has an unmodulated center frequency of 10.7 MHZ. (a) To what frequency must the VCO be set (b) From which circuit is the recovered modulating signal taken
what is the linear dynamic range of the amplifier?
Determine the periods and find exponential fourier series coeffecients of functions. A.) f(t) = 2(cost)(cos2t) B.) g(t) = 3 + 2e^-j2t + 2e^j2t + 2cos4t C.) h(t) = 4
1. Determine the capacitance for a capacitorif its impedance is 5000 ohms at 400 radians/second. 2.Calculate the frequency that will cause a100mH inductor to have an impedance of 15,708 ohms.
A triangular loop is placed in the x-z plane. Assume that a dc current, I = 2A ,flows in the loop and that B = 30az mWb/m exists in the region. Find the forces and the torque on the loop.
A photocell with a 35-ms time constant is used to measure light flashes. How long after a sudden dark-to-light flash before the cell output is 80% of the final level
Design a clock that displays seconds from 0 to 30 on the FPGA 7-segment displays, with a reset button that resets the clock value at any time.
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