Reference no: EM132224988

Question 1. Statistical Process Control

THE DATA IN THE FOLLOWING TABLES ARE AVAILABLE IN AN EXCEL SPREADSHEET (HW3-Quality Data.xlsx)

The Los Angeles Metro Rail Authority commissioned a study of travel time variation between two heavily used but adjacent subway stations (A and B) in the city. The following table shows observations in seconds of the time for travel between the two stations over a two-week period (each day 5 observations were collected).

(a) Based on the above table, calculate the upper and lower control limits and the center-lines for the mean (X¯) and range (R) charts. Use the "factors" given in your slides (from Asynch Session 5).Control chart factors are also in the associated Excel data file.

(b) A few weeks after the limits and average case performance were established and agreed upon by the study team, the Authority commissions another round of observations (see below) to determine the process capability and control. Is the process governing travel times (between those two stations) in control? Why or why not?If the process is out of control, provide all reasons.

(c) Suppose the scheduling team within LA Metro specifies that the minimum and maximum travel times between the stations be 106 and 116 seconds respectively, determine whether the process is capable based on the observations in part (b). Also, was the process performance capable to begin with in part (a)?

(d) If LA Metro wants to achieve a capable process for this segment (in terms of travel times between Stations A and B), what is their maximum allowable based on the data in part (b)?

Control Chart Factors

Question 2. TechZoom Semiconductor Manufacturing

TechZoom semiconductor company's basic manufacturing process involves building circuitry on a single silicon wafer one layer at a time. The same basic 5 steps (with variations dictated by the circuit design) are repeated for as many layers as needed, in this case 12 layers. Please see the process map below.

The five steps completedin each layer are:
a) Electrochemical Deposition, where coats of conductive materials are applied to the wafer substrate
b) Lithography, where circuit patterns are imaged onto the coated wafers
c) Etching, where the circuitry is embossed by dissolving the coat selectively
d) Doping, or Ion implantation, where different parts of the circuit are given special characteristics
e) Furnaces, where the doped regions of the circuits are activated for circuit function

A wafer has with slots for 500 chips or die each. When the 12-layer circuit is completed, the wafer is sliced to obtain the 500 die, which are then individually packaged in a die-packaging facility. However, after each layer is built, because of contaminants or other quality defects,an average 2% of the die are rejected or marked as unusable. So, at the end, when the wafer is sliced, we only obtain a fraction of the 500 die we started with, that can be packaged and shipped to customers.

There is a dedicated machine for each step, so each layer corresponds to a repeat visit by the wafer to that machine for that step. Since the wait times are not infinite (no matter how lengthy), you can assume less than 100% utilization at machines for each step. Demand for the company's chips is at the rate of 7500 good quality die/day. The factory operates 24 hours / day, 7 days / week.

(a) What is the total WIP (in wafers) in the factory? Also, report the average number of wafers in queue at each of the major steps?

(b) Each wafer is valued at $25,000, and the holding cost is 15% of the value of the wafer per year. What is the total annual inventory holding cost for the factory?

(c) Suppose with better information systems and scheduling systems, the wait times are reduced by 20% at each of the major steps (processing times remain unchanged). What is the savings in annual inventory holding cost for the factory?

Attachment:- homework.rar