What is the speedup achieved by adding this improvement

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Reference no: EM133424130

Question: When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the performance and cost. Assume that we are starting with the single cycle datapath seen in class, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400 ps, 100 ps, 30 ps, 120 ps, 200 ps, 350 ps, and 100 ps, respectively.

Consider the addition of a multiplier to the ALU. Th is addition will add 300 ps to the latency of the ALU but will reduce the number of instructions executed by 5% since we will no longer need to emulate the MUL instruction.

a) What is the clock cycle time with and without this improvement?

b) What is the speedup achieved by adding this improvement?

Reference no: EM133424130

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