What is the shortest clock cycle

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Reference no: EM133455152

Question: Consider the 5-stage pipelined MIPS datapath that implements a subset of the MIPS instruction set (R- format, Lw, Sw, beq). Assume the following latencies for the major functional units: 200 ps for instruction memory access, 150 ps for ALU operation, and 100 ps for register file access and 300 ps for data memory access.

. What is the shortest clock cycle?

. What is the latency of a sw instruction?

. If we split one of the 5-stages into 2 equal stages in the pipelined design to decrease the clock cycle, which stage should we split? What would be the new clock cycle?

Reference no: EM133455152

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