Reference no: EM133517729

Question: The system employs a 1 MB 2-way set associative cache with 128-byte cache lines. It also uses a 32-bit CPU-to-memory data bus as well as 32-bit physical addresses. Each memory module requires 4 clock cycles to perform either a read or a write operation.

a] Assuming that the memory system is low order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each ?eld in bits. Also describe how each field is used.

b] Assuming that the memory system is high order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each field in bits. Also describe how each field is used.

c] 'What is the minimum number of clock cycles required to fill a cache line ifthe memory system is low order interleaved?

d] What is the minimum number of clock cycles required to ?ll a cache line ifthe memory system is high order interleaved?