What is the minimum number of clock cycles required to fill

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A byte-addressable memory system contains?fgur memory modules each of which is 32 bits wide by 228 cells deep. The system employs a 1 MB 2-way set associative cache with 128-byte cache lines. It also uses a 32-bit CPU-to-memory data bus as well as 32-bit physical addresses. Each memory module requires 4 clock cycles to perform either a read or a write operation.

Question a] Assuming that the memory system is low order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each field in bits. Also describe how each ?eld is used.

Question b] Assuming that the memory system is high order interleaved, show the proper 32-bit format for physical addresses, including the required fields, the width of each field in bits. Also describe how each field is used.

Question c] What is the minimum number of clock cycles required to fill a cache line if the memory system is low order interleaved?

Question d] What is the minimum number of clock cycles required to fill a cache line if the memory system is high order interleaved?

Reference no: EM133516690

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