Reference no: EM131754509

Assignment

1. Assume the stages of a pipelined architecture have the following latencies:

IF	ID	EX	MEM	WB
210 ps	220 ps	250 ps	200 ps	200ps

a. What is the clock cycle time in this pipelined architecture?

b. What is the clock cycle time assuming the architecture is not pipelined?

c. Assuming a Store Word instruction passes through this pipeline, and doesn't actually use hardware in the Write Back phase, what is the latency of the instruction?

d. If we can split one stage of the pipeline into two, each with half the latency of the former stage, which stage would you split, and what is the new clock cycle time?

e. Assuming 1000 arithmetic instructions are executed consecutively with no branches being taken, what is the time required to complete these instructions? Remember, the pipeline is not full when you start and when you finish.