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Question: Consider two different implementations of the same MIPS instruction set architecture. The instructions can be divided into three classes according to their CPI (R- type, I-type, J-type). P1 with a clock rate of 2.8 GHz and CPIs of 1.4, 2.8, and 3.1; and P2 with a clock rate of 3.5 GHz and CPIs of 2.6, 3.3, and 3.8. Given a program with a dynamic instruction count of 5.0E6 instructions divided into classes as follows: 50% R- type, 25% I-type, 25% J-type, which implementation is faster and by how much?
a. What is the global CPI for each implementation?b. Find the clock cycles required in both
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