Reference no: EM131756214

Architecture Assignment

1. The representation for floating point that we learned is single precision. In that IEEE 754 floating point format, represent the decimal value 63.25.

2. Represent the decimal value -1.125 in our IEEE 754 floating point format.

3. What result am I likely to get by adding 1E10 and 1E-32 in our architecture, using IEEE 754 single precision? Why?

4. Suppose that I have a list of n random values, ranging from 1E-32 to 1E10 in size. Assume I have lots of values at each available order of magnitude. If I wish to calculate the most accurate sum that I can within the limitations of our architecture, what is one simple thing I can do to make the sum more accurate?

5. Suppose we have a 5 stage pipeline with our MIPS architecture. The latencies of the pipeline states are 250ps for IF, 350ps for ID, 150ps for EX, 300ps for MEM, and 200ps for WB. Further, a program we wish to run has 45% arithmetic instructions, 20% branch instructions, and 35% load/store instructions.

a. What is the clock cycle time for both pipelined and non-pipelined processors?

b. What is the total latency of a load instruction in each of a pipelined and non-pipelined processor?

c. If we could split one stage of the pipelined processor into two stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

d. Suppose we can double the number of registers. Doing so would reduce the number of load/store instructions by 10% for the program above, but increase the register latency by 50ps.

i. What is the speedup achieved by this proposed improvement?
ii. What effect could this change have on the number of instructions represented in the architecture?