What is the capacitance of the oxide layer per unit area

Reference no: EM131321099

A distortion is observed in the experimental HFCV curve of the 100A-oxide p-MOSC in problem after it is stressed in a very high electric field (about V_G=8V). The distortion is indicated by the non-equal voltage shifts observed at two capacitances. C=0.9C_o and C=0.8C_o, and are ?V_G0.9 =+1.000V and ?V_G0.8 = +1 100V What is Gp. the interface state density generated during this stress and what is the range energy levels of these interface states?

Problem:-

The n-channel Si MOS transistor switch In the DRAM (dynamic random access) cell of the next generation 16 Mbit chip (1 bit = 1 cell which contains 1 transistor and 1 capacitor) requires an oxide of 100A or 10nm (IA =10^-8cm = 0.1nm and 1nm 10^-9m = 10^-7cm = 10A).

The cell sizes or lithographic line width are about 0.7μm 7000A = 700nm in order to pack 16 million cells on one 0.5cmx0.5cm chip. This small line width requires low temperature processing so that the high temperature oxidation and diffusion times are not so short to be controllable. Suppose that the 100A thick oxide is to be grown at 900C in dry oxygen on a p-type SI.

(a) What is the oxidation time in seconds.

(b) What is the capacitance of the oxide layer per unit area, C°, in pF/cm²?

Reference no: EM131321099

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