What is meant by the term partial address decoding

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Reference no: EM131531257

Question: 1. What is meant by the terms partial address decoding and full address decoding?

2. A microcomputer designer decides to implement the simplest possible partial address decoder. Three 1-Mbyte blocks of memory are arranged so that the first block is selected when A23 1, the second when A22 = 1 and the third when A21 = 1. This decoder is so simple that it is nonexistent! The designer simply connects the appropriate address line (i.e. A21 or A22 or A23) to the memory block's CS* input via an inverter. Would this arrangement work? What, if any, are the dangers inherent with this system?

Reference no: EM131531257

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