What happens in stages d e m for a store instruction sw

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Reference no: EM131479737

Assignment

1) A)Assume that registers are written in the 1st half of the clock cycle, read in the 2nd half. Show cycle by cycle execution of the following code segment. Identify every possible type of hazard, mark the hazards by arrows. The processor does not use forwarding, resolve all hazards by stalling. Shows stalls as letter "S" in an appropriate cycle. Execute all instructions shown after the branch is resolved. The branch is not taken (after it is resolved).

Instr/Clock Cycle
                          1   2     3     4     5
Xor    R4,    R5,    R9     IF    ID    Ex    M    Wb
Add    R1,    R1,    #4
Sub    R6,    R5,    R4
BNE    R1,    R7,    L_
Ld      R5,    52 (R6)
St      R6,    8 (R4)
Sub    R7,    R5,    R4
Add    R2,    R5,    R7
...
L_:

B) Same as 1) but now the processor supports forwarding on data hazards. Show the cycle by cycle execution.

2) a)Same as b) but now assume a branch delay slot. Reorder instructions to reduce stalls on control hazards. Show the new code and its cycle by cycle execution.

b) Write the RTL code describing what happens in stages D, E, M for a store instruction SW.

Reference no: EM131479737

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