What fraction of bus cycles are available for dma transfer

Assignment Help Basic Computer Science

Reference no: EM13307938

A computer consists of a processor and an I/O device D connected to main memory M via a shared bus, with a data bus width of one word. The processor can execute a maximum of 2.0 × 107 instructions per second. Suppose that the processor is continuously executing "background" programs that require 90% of its instruction execution rate, but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D.

If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in million of words per second, possible through D while the background programs are running. million words /sec

Now suppose that an average instruction requires 6 machine cycles, 4 of which use the memory bus. A memory read or write operation uses one bus cycle. A DMA controller can use all the bus cycles not used by the "background" programs, and also can utilize cycles which are unused by background programs. Thus, while background programs are not running (10% of the time), all of the cycles are available. When background programs are running (90% of the time), 2 out of 6 bus cycles, are available for DMA transfer.

What fraction of the bus cycles are available for DMA transfer?

Estimate the maximum transfer rate if DMA is used. For DMA access, assume one word is transferred for each bus cycle, and ignore any setup or status-checking time. Your answer from part B should be helpful for this calculation. million words /sec

Reference no: EM13307938

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