Reference no: EM132940040

Computer Architecture & Organization Assignment

Note the following:

1. All questions should be attempted by each individual student and copy/paste is strictly prohibited. Those who do not follow the instructions, will be marked zero in their respective assignments.

2. As this is part of semester course assessment's, it should be submitted through LMS only and within due date. Assignment submitted after the deadline will not be accepted nor graded.

3. Answer the questions in your own neat handwriting and scan & submit it through LMS.

Q1. a. How many 128 x 8 memory chips are needed to provide a memory capacity of 4096 x 16?

b. A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The physical address size is 32 bits, and the smallest addressable unit is 1 byte.
I. Draw a diagram showing the organization of the cache and indicating how physical addresses are related to cache addresses.
II. To what block frames of the cache can the address 000010AF16 be assigned?
III. If the addresses 000010AF16 and FFFF7Axy16 can be simultaneously assigned to the same cache set, what values can the address digits x and y have?

Q2. Briefly explain the followings:
a. Differentiate between tightly coupled and loosely coupled microprocessor from the viewpoint of hardware organization and programming techniques?
b. What is cache coherence and why it is important in shared memory multiprocessors system?
c. How many lines of the address bus must be used to access 2048 bytes of memory? How many of these lines will be common to all the chips?
d. Explain with the help of flow diagram how an instruction is fetched, decoded and executed?
e. What are the advantages of assembly language? How is it different from high- level language?