Reference no: EM133354239

Question

We are interested in two implementations of two similar but still different ISA, one with and one without special real number instructions. Both machine have 1.5GHz clock. Machine With Floating Point Hardware - MFP implements real number operations directly with the following characteristics: -real number multiply instruction requires 6 clock cycles - real number add instruction requires 4 clock cycles - real number divide instruction requires 20 clock cycles Any other instruction (including integer instructions) requires 2 clock cycles Consider Program P with the following mix of operations: - real number multiply 10% - real number add 15% - real number divide 5% - other instructions 70%.