Wait states for proper system operation bus clocking rate

Reference no: EM13101224

Let the microprocessor which has a memory read timimg. After some analysis, designer determines that memory falls short of giving read data on time by about 180 ns.

a. How many wait states (clock cycles) require to be inserted for proper system operation if bus clocking rate is 8 MHz?
b. To reinforce wait states, a Ready status line is employed. Once processor has issued Read command, it should wait until Ready line is asserted before trying to read data. At what time interval should we keep Ready line low in order to force processor to insert required number of wait states?

Reference no: EM13101224

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