Reference no: EM133295353
1. To support full data forwarding, the number of forwarding paths in a hypothetical 7-stage pipeline implementation of the MIPS processor is larger than the number of such paths in the "MIPS" 5-stage pipeline.
True False
2. A processor executing several scientific applications that have the same frequencies of the different floating-point instructions, will exhibit the same MFLOPS rating for all these applications.
True False
3. The sign-extension circuit in the ID stage of the 5-stage MIPS pipeline is used only in ALU instructions with an immediate operand.
True False
4. On the 5-stage "MIPS" pipeline processor, no data forwarding will be needed during the execution of a program that has undergone static scheduling by an optimizing compiler.
True False
5. Out of the following two alternatives for implementing a pipelined multiplier, the first alternative will always perform "better". Alternative 1: Three stages with circuit delays of 1.1ns, 1.35ns and 1.2ns.
Alternative 2: Five stages with circuit delays of 0.7ns, 0.8ns, 0.9ns, 1.0ns and 1.0ns. You may ignore the delay of inter-stage latches and define "better" appropriately!
True False