Two alternatives to the mesi protocol are moesi

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Reference no: EM13503729

Two alternatives to the MESI protocol are MOESI (used in AMD processors) and MESIF (first) used in Intel's Nehalem processor. If there's a shared bus like the Front Side Bus in which all processors can report their snoop results at the same time, MESI is practical.However, if additional bus cycles or overhead is required for each processor to report a snoop result, MESIF may be employed.
The essential difference between MESIF and MESI is that in MESIF if a line is shared, a single processor (the one with the line in F or "forward" state )has responsibility for providing the data if another processor does a read operation. Processors that have the line in shared (S) state still respond but do not provide the data. This reduces coherence--related traffic and reduces latency since a cache can produce the required data faster than DRAM. When the processor with the line in the forward state reports its result to another processor, it moves the line to "shared" state and the cache with the new copy of the cache line puts it in the "forward" state. So the job off forwarding is transferred to the last processor to broadcast a read request.

Draw the state transition diagram for the MESIF protocol. Present it as two diagrams: one for the snooping processor and another for the processor being snooped. Use the same convention used in class to describe the MESI protocol. For transitions that occur when the processor is performing an operation that is being snooped, each transition arc should indicate the CPU operation requested, the bus operation performed in response to the CPU request, and the snoop response. For transitions the occur when the processor is snooping each arc should indicate the bus operation being snooped, the snoop response the processor will report, and any bus operation the processor will perform.
Think how you might simply modify the MESI state diagrams from the lecture to accommodate the new state and behavior.
For bus operations use

RFO Read for Ownership
Read Read from DRAM
WriteBack Write to DRAM (may also be "snarfed" by another processor)

•Forward For forwarding a line to another cache;doesn't write to memory

Reference no: EM13503729

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