The mips architecture reserves register

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Reference no: EM13168151

The MIPS architecture reserves register 0 (called $zero) to be always equal to 0. This allows synthesizing additional addressing modes and additional instructions from the instruction set.
The 'load' instruction in MIPS that transfers data from the memory to a register supports only the 'base
with displacement' addressing mode. This is the format of the 'lw' (load word) instruction:
lw <reg>, <imm>(<reg>)

An example is: lw t0, 12(s0)

the data in the memory at address (s0+12) is copied into register t0.

Part a) Show how the addressing mode above can be used as the 'direct addressing' mode.

Part b) Show how the addressing mode above can be used as the 'register indirect addressing' mode.

Part c) Show how the register $zero can be used to synthesize a 'mov' instruction from the 'add'
instruction. The 'mov' instruction copies one register into another. The 'mov' instruction will then be a
pseudoinstruction. (Syntax: mov <reg>, <reg> add <reg>, <reg>, <reg>)

Part d) Show how the register $zero can be used to synthesize a 'li' (load immediate) instruction from the
'addi' (add immediate) instruction. The 'li' instruction loads an immediate number in a register. (Syntax:
li <reg>, <constant> addi <reg>, <reg>, <constant>)

Part e) In your opinion, do the uses above justify reserving a register to be always equal to zero?

Reference no: EM13168151

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