The enhancement load transistor in the nmos inverter

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Reference no: EM131228082

The enhancement-load transistor in the NMOS inverter in given Figure has a separate bias applied to the gate. Assume transistor parameters of K_n = 1 mA/V₂for M_D, K_n = 0.4 mA/V₂ for M_L, and V_{T N} = 1 V for both transistors. Using the appropriate logic 0 and logic 1 input voltages, determine V_O _H and V_O _L for:

(a) V_B = 4 V,

(b) V_B = 5 V,

(d) V_B = 7 V.

57_Figue 2.jpg

Reference no: EM131228082

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