The data bus of a microprocessor system

Reference no: EM131074103

b) RD and MEMRQ are control lines from the CPU. What must their logic state be in order to read the switches?

4. FIGURE 1 shows how a 3 to 8 line decoder (74138) can be used in conjunction with NAND gate (74133) to connect a set of switches to the data bus of a microprocessor system via buffers (74367).

Answer the following questions relating to the diagram:

a) What address, in HEX, is required on the address bus in order to read the switches?

Reference no: EM131074103

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