Reference no: EM13836185
In this problem you will design a Moore finite state machine that realizes a synchronous 3-bit counter with a mode control input M and three outputs QA, QB, and Qc. When M = 0, the counter output advances through the 3-bit numbers using a step size of 2. When M = 1, the counter advances through the 3-bit numbers using a step size of 3.
1. Represent the Moore finite state machine by completing the state table in Figure.
Figure 1: State table for a synchronous 3-bit counter with a mode control input M.
2. Sketch the corresponding state diagram.
3. Given that the state machine is realized using D-type flip-flops, obtain logic equations in terms of M, QA, QB, and QC for the flip-flop inputs DA, DB, and DC using the four-variable Karnaugh map.
- You must use the format of the four-variable Karnaugh map do not interchange the position of the variable M, QA, QB, and QC.
- Include one four-variable Karnaugh map for each b-type Hip-flip input.
- In each K-map, circle the miniterms corresponding to each term in your expression for the D input.
4. Draw the logic circuit that realizes the signal DA in terms of M, QA, QB and QC using NAND gates. Do not realize logic circuits for the remaining inputs DB and DC.
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