Subtract sequential restoring divider for unsigned integers

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Question 1. Develop an RTL VHDL description of the Shift/subtract sequential restoring divider for unsigned integers. The circuit generates a correct result (quotient q and remainder r) only for the case of the following relation between the dividend z and the divisor d: z7..4 < d.

Question 2. Write Testbench Code covering all possible values of inputs a and x, and reporting any discrepancies between the actual and expected outputs.

Reference no: EM133295390

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