Reference no: EM131232891

Logic Circuits Assignments

Problem 1: Given the following sequence detector:

a) What kind of finite state machine is this:

b) Using a procedure by inspection can you state which sequences does this circuit detect?

c) Modify the circuit's shift register so the shift register uses SR Flip Flops instead of D FF, without changing the rest of the output circuitry.

d) Modify the circuit's shift register so the shift register uses T- Flip Flops instead of D Flip Flops, without changing the rest of the output circuitry.

Problem 2: Design a sequential circuit that counts consecutive or non-consecutive ones in a binary input sequence, from 1 to 3 and then repeats. Use one JK Flip Flop first and one D Flip Flop last.

a) State Diagram of your counter:

b) State Table from above State Diagram

c) Augmented State Table using the Requested Flip Flops

d) Karnaugh Maps for each Flip Flop input and minimal SOP expressions for such inputs.

J1 =                                                        K1 =                                                             D2 =

Now try to manipulate these expressions so that the discrete gate count at the input is minimized.

e) Including the final circuit for your design trying to minimize the discrete gate count at the Flip Flop inputs.

Problem 3: Design an up and down counter that counts up  (0,1,2,3,0,1,2 ... etc) when an input x is 0 and counts down (3,2,1,0,3,2 ...etc) when the input x is 1. Use one SR Flip Flop first and one T Flip Flop last.

a) State Diagram for your Counter

b) State Table from the above State Diagram

c) Augmented State Table including the required Flip Flops

d) Karnaugh Maps and minimal SOP expressions for the input to each Flip Flop.

S1 =                                                        R1 =                                                                       T2 =

Now try to manipulate the minimal SOP expressions so that the discrete gate count can be minimized.

S1 =                                                        R1 =                                                                       T2 =

e) Final circuit for your design trying to minimize discrete gate count at the input of each Flip Flop.

Problem 4: Design a Counter that counts even numbers 0,2,4,6,0,2,4,6 ... etc when input x is 0 and counts odd numbers 1,3,5,7,1,3,5 ... etc when input x is 1. If input changes in the middle of a counting sequence Counter goes to next value of the other sequence. For example, if with input x=0 is counting 0,2,4 and the input changes to x=1, it continues with 5,7... etc. If with input x=1 is counting 1,3,5 and the input changes to x=0, it continues with 6,0,2 ... etc. Use only JK Flip Flops.

a) State Diagram for your Counter

b) State Table from the above State Diagram

c) Augmented State Table including columns for the input of each Flip Flop.

d) Kaurnaugh Maps to minimize SOPthe expressions at the input of each Flip Flop. Manipulate the minimal SOP so as to minimize discrete gate count.

J1 =                                                                        K1 =                                                                       J2 =

K2 =                                                                       J3 =                                                                        K3 =

Try to manipulate each minimal SOP expression so as to minimize discrete gate count if possible:

J1 =                                                                        K1 =                                                                       J2=

K2 =                                                                       J3 =                                                                        K3 =

e) Final circuit trying to minimize discrete gate count at the input of each FF.