Reference no: EM13218249
A. Consider a Si PMOS capacitor with NA=10^17cm-3 , x0=10nm, and a heavily doped p+ Poly-Si gate.
B. Consider a Si NMOS capacitor with ND=10^17cm-3, x0=10nm, and a heavily doped n+ Poly-Si gate.
a. For the PMOS, calculate the applied voltage and the electric field (at the Si-SiO2 interface) to make the silicon surface intrinsic. What is the depletion width in this case?
b. With no oxide fixed or mobile charges and no interface traps, calculate the threshold voltage for both PMOS and NMOS.
c. If HfO2, a high-k dielectric with εr=25 is to be used instead of SiO2 as the gate oxide, what is the thickness of HfO2 required to obtain the same threshold voltage as that in (b) for any of the devices (or the same oxide capacitance). This thickness is called the EOT or oxide equivalent thickness.
d. For a fixed oxide charge density Qf/q=5x1011cm-2 located as a charge sheet at 5nm from the SiO2-Si interface, and for a fixed interface trap density of 1012cm-2 at the SiO2-Si interface (assume fixed quantity with time and applied voltages), calculate the threshold voltage for both devices.
e. Sketch the Capacitance-Voltage characteristics for both devices based on part (d) by giving appropriate labeling to the voltage and capacitance axis. You may assume high f measurements.
f. A fixed voltage VB is to be applied to the substrate electrode. Calculate VB for both devices such that their flatband voltage found in (d) equals zero.
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