Reference no: EM13857495

1) The SOP expression for c8 in a carry-lookahead adder is

c₈ = _^g7 + p₇g₆ + p₇p₆g₅ + p₇p₆p₅g₄ + p₇p₆p₅p₄g₃ + p₇p₆p₅p₄p₃g₂+
+ p₇p₆p₅p₄p₃p₂g₁ + p₇p₆p₅p₄p₃p₂p₁g₀ + p₇p₆p₅p₄p₃p₂p₁p₀c₀

Show how to implement this expression if only gates with at most 4 inputs can be used. Rewrite the expression for c₈ using parentheses to show the associated grouping of inputs. Sketch and label the corresponding circuit and determine its cost. The ?rst priority for optimization is to keep the longest delay from any of the inputs to the c₈ output as short as possible. The second priority is to minimize the cost of the circuit. Compare the longest delay from input to output and the cost of your circuit to the cost and delay of a direct SOP implementation (without gate input constraints) for c₈.

Attachment:- digital logic.zip